NXP Semiconductors /LPC18xx /RTC /ERCONTRO

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Interpret as ERCONTRO

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)INTWAKE_EN0 0 (DISABLED)GPCLEAR_EN0 0 (NEGATIVE)POL0 0 (DISABLED)EV0_INPUT_EN 0RESERVED0 (DISABLED)INTWAKE_EN1 0 (DISABLED)GPCLEAR_EN1 0 (NEGATIVE)POL1 0 (DISABLED)EV1_INPUT_EN 0RESERVED0 (DISABLED)INTWAKE_EN2 0 (DISABLED)GPCLEAR_EN2 0 (NEGATIVE)POL2 0 (DISABLED)EV2_INPUT_EN 0RESERVED0 (DISABLE_EVENT_MONITO)ERMODE

INTWAKE_EN1=DISABLED, ERMODE=DISABLE_EVENT_MONITO, GPCLEAR_EN0=DISABLED, INTWAKE_EN2=DISABLED, POL0=NEGATIVE, EV1_INPUT_EN=DISABLED, POL2=NEGATIVE, EV2_INPUT_EN=DISABLED, INTWAKE_EN0=DISABLED, EV0_INPUT_EN=DISABLED, GPCLEAR_EN2=DISABLED, GPCLEAR_EN1=DISABLED, POL1=NEGATIVE

Description

Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup.

Fields

INTWAKE_EN0

Interrupt and wake-up enable for channel 0.

0 (DISABLED): No interrupt or wake-up will be generated by event channel 0.

1 (ENABLED): An event in channel 0 will trigger an (RTC) interrupt and a wake-up request.

GPCLEAR_EN0

Enables automatically clearing the RTC general purpose registers when an event occurs on channel 0.

0 (DISABLED): Channel 0 has no influence on the general purpose registers.

1 (ENABLED): An event in channel 0 will clear the general purpose registers asynchronously.

POL0

Selects the polarity of an event on input pin WAKEUP0.

0 (NEGATIVE): A channel 0 event is defined as a negative edge on WAKEUP0.

1 (POSITIVE): A channel 0 event is defined as a positive edge on WAKEUP0.

EV0_INPUT_EN

Event enable control for channel 0. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.

0 (DISABLED): Event 0 input is disabled and forced high internally.

1 (ENABLED): Event 0 input is enabled.

RESERVED

Reserved. Read value is undefined, only zero should be written.

INTWAKE_EN1

Interrupt and wake-up enable for channel 1.

0 (DISABLED): No interrupt or wake-up will be generated by event channel 1.

1 (ENABLED): An event in channel 1 will trigger an (RTC) interrupt and a wake-up request.

GPCLEAR_EN1

Enables automatically clearing the RTC general purpose registers when an event occurs on channel 1.

0 (DISABLED): Channel 1 has no influence on the general purpose registers.

1 (ENABLED): A n event in channel 1 will clear the general purpose registers asynchronously.

POL1

Selects the polarity of an event on input pin WAKEUP1.

0 (NEGATIVE): A channel 1 event is defined as a negative edge on WAKEUP1.

1 (POSITIVE): A channel 1 event is defined as a positive edge on WAKEUP1.

EV1_INPUT_EN

Event enable control for channel 1. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.

0 (DISABLED): Event 1 input is disabled and forced high internally.

1 (ENABLED): Event 1 input is enabled.

RESERVED

Reserved. Read value is undefined, only zero should be written.

INTWAKE_EN2

Interrupt and wake-up enable for channel 2.

0 (DISABLED): No interrupt or wake-up will be generated by event channel 2.

1 (ENABLED): An event in channel 2 will trigger an (RTC) interrupt and a wake-up request.

GPCLEAR_EN2

Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2.

0 (DISABLED): Channel 2 has no influence on the general purpose registers.

1 (ENABLED): An event in channel 2 will clear the general purpose registers asynchronously.

POL2

Selects the polarity of an event on input pin WAKEUP2.

0 (NEGATIVE): A channel 2 event is defined as a negative edge on WAKEUP2.

1 (POSITIVE): A channel 2 event is defined as a positive edge on WAKEUP2.

EV2_INPUT_EN

Event enable control for channel 2. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.

0 (DISABLED): Event 2 input is disabled and forced high internally.

1 (ENABLED): Event 2 input is enabled.

RESERVED

Reserved. Read value is undefined, only zero should be written.

ERMODE

Controls enabling the Event Monitor/Recorder and selecting its operating frequency. Event Monitor/Recorder registers can always be written to regardless of the state of these bits. Events occurring during the 1-sec interval immediately following enabling of the clocks may not be recognized.

0 (DISABLE_EVENT_MONITO): Disable Event Monitor/Recorder clocks. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected.

1 (16_HZ_SAMPLE_CLOCK): 16 Hz sample clock. Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out.

2 (64_HZ_SAMPLE_CLOCK): 64 Hz sample clock. Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out.

3 (1_KHZ_SAMPLE_CLOCK): 1 kHz sample clock. Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out.

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